This invention relates, in general, to semiconductor memory devices and more particularly, to electrically alterable, nonvolatile floating gate memory devices.
The microprocessor based systems, as well as the related arts, has long required electrically alterable read only memory (EAROM) elements that were nonvolatile and many such devices have, to some extent, filled this need. However, as the computer arts have become more complex in nature and have required high speeds and greater capacity there now exists the need for a high density memory device that may be easily programmed or "written" and, as the occasion arises, to reprogram ("erase" and "rewrite") the device in the field. To this end, devices are presently available to the design engineers that exhibit nonvolatile characteristics but, as will be discussed, they have inherent shortcomings that are overcome by the subject invention.
One such device resides in the family of Floating Gate Avalanche Metal Oxide Semiconductor (FAMOS) devices. The advantage of this type of device resides in the fact that it is independent of any outside current to maintain the stored information in the event power is lost or interrupted. Since these devices are independent of any outside power there is also no need to refresh the device which feature results in a significant savings in power.
The floating gate family of devices usually has source and drain regions of a given conductivity type, formed in a substrate of the opposite conductivity type, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is formed by first applying a thin insulating layer followed by a conductive layer (the floating gate) followed by a second insulating layer in order to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (usually referred to as the control gate) is formed over the second insulating layer (in the region of the floating gate) to complete the gate structure. Such devices are exemplified in U.S. Pat. No. 3,500,142 issued to D. Kahng on Mar. 10, 1970 and U.S. Pat. No. 3,660,819 D. Frohman-Bentchkowsky on May 2, 1972. The major drawback of these devices resides in the fact that high fields are required to produce the necessary avalanche breadkdown in order for charge to be placed on the floating gate. Further, to erase the charge appearing on the floating gate, the entire device must be provided with a transparent window so that the chip may be flooded with energy in the ultra violet or x-ray portion of the spectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the device then requiring that the entire chip be completely reprogrammed. Further, the erasing step required an extremely long period of exposure time, of the order of about 30 to 45 minutes, with the device or chip removed from the equipment.
In recent years, the art has progressed to the point where nonvolatile floating gate read only memory devices have been produced and which are electrically alterable. One such memory cell has been described in detail in an article entitled "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage" by W. S. Johnson, et al., ELECTRONICS, Feb. 28, 1980, pp. 113-117. In this article the authors describe a "Floating-Gate Tunnel Oxide" structure wherein a cell using a polycrystalline silicon (polysilicon) floating gate structure is charged with electrons (or holes) through a thin oxide layer positioned between the polysilicon gate and the substrate. The Fowler-Nordheim tunneling mechanism is used to charge the polysilicon gate. An elevation view of a typical device is described, and shown in FIG. 1 of the article, wherein the floating gate member represents the first polysilicon level. By using this type of structure (a structure wherein the first level polysilicon represents the floating gate and is closest to the substrate, covered by a second polysilicon level) an inordinately high floating gate-to-substrate capacitance is produced. This area of floating gate is necessary in order to maintain close coupling between the first polysilicon level and next deposited or second polysilicon level. It has been found that some manufacturers find it necessary to etch away portions of the first polysilicon level in order to reduce the capacitance between the floating gate and the substrate without substantially reducing the capacitance between the first and second polysilicon levels.